Lab for High Performance Computing SERC, Indian Institute of Science
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Lab Alumni

Ph.D.

  1. Jayvant Anantpur, Enhancing GPGPU Performance through Warp Scheduling, Divergence Taming and Runtime Parallelizing Transformations, November 2017
  2. Sreepathi Pai, Efficient Dynamic Automatic Memory Management and Concurrent Kernel Execution for General-Purpose Programs on Graphics Processing Units, December 2014
  3. R Manikantan, Improving Last-Level Cache Performance in Single and Multi-Core Processors, October 2012
  4. Rupesh Nasre, Scaling Context-Sensitive Points-to Analysis, February 2012
  5. T.S. Rajesh Kumar, On-Chip Memory Architecture Exploration of Embedded System on Chip, September 2008
  6. Kaushik Rajan, Efficient Cache Organization for Application Specific and General Purpose Processors, September 2008
  7. V. Santhosh Kumar, Improving the Communication Performance of I/O Intensive and Communication Intensive Applications in Clusters, October 2007

M.Sc. (Engg.)

  1. Adarsh Patil, Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Systems, July 2017
  2. Vaivaswatha N, Fast Flow-Sensitive Pointer Analysis, August 2014
  3. Prasanna Pandit, Cooperative Execution of OpenCL Programs on Multiple Heterogenous Devices, November 2013
  4. Ashwin Prasad, Automatic Compilation of MATLAB Programs for Synergistic Execution on Heterogeneous Processors, January 2012
  5. Abhishek Udupa, Efficient Compilation of Stream Programs for Multicores with Accelerators, July 2009
  6. Aditya Thakur, Comprehensive Path-sensitive Data-Flow Analysis, January 2009
  7. Girish B.C., Efficient Techniques Exploiting Memory Hierarchy to Improve Network Processor Performance, June 2008
  8. Santosh G. Nagarakatte, Spill Code Minimization and Buffer and Code Size Aware Instruction Scheduling Technique, January 2008
  9. Rajesh Vivekanandham, Scalable Low Power Issue Queue and Store Queue Design for Superscalar Processors, December 2006
  10. Sudhakar Surendran, A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs, November 2006
  11. Govind Shenoy, Performance Modeling and Evaluation of Network Processors, July 2006
  12. Shyam Krishnaswamy, Power-Aware Compilation Techniques for Embedded Systems, July 2006
  13. Sarvani V. V. N. S., Compiler Techniques for Code Size and Power Reduction for Embedded Processors, July 2004
  14. A Radhika Sarma, A Simple Replacement Policy and a Dynamic Prefetching Technique for WWW Cache, April 2004
  15. Subash Chandar G., Reconfigurable Architectures for Application Specific Processors used in Embedded Control Applications, February 2002
  16. K. V. Manjunath, Performance Analysis of Methods that Overcome False Sharing Effects in Software DSMs, April 2001
  17. Manoj N. P., CAS-DSM: A Compiler Assisted Software Distributed Shared Memory System, April 1999
  18. V. Janaki Ramanan, Efficient Resource Usage Modelling, April 1999
  19. Vinnakota Sricharan, Study of Cache and TLB Performance in a Distributed Virtual Shared Memory System, April 1999
  20. Madhavi G. Valluri, Evaluation of Register Allocation and Instruction Scheduling Methods in Multiple Issue Processors, January 1999

M. Tech.

  1. R. Karthikeyan, A Multi-Stage Linear Regression Strategy for Determining Rmax of a TOP500 System, July 2008
  2. S. Sujatha, A Clustered Digital Library Server with Cooperative Semantic Cache, January 2002
  3. Anand Chitipothu, DOMP: OpenMP Programming on Cluster of SMPs, January 2002

M.E. (Reg.)

  1. Arth Patel Kausheybhai, Improving Memory Hierarchy Performance in Heterogeneous System Architecture (HSA), July 2015
  2. R. Manikantan, Performance Enhancement Schemes for Superscalar Processors: Exploiting Narrow Width Results and Limited Prefetching, June 2006
  3. Rajani Pai, FEADS: A Framework for Exploring the Application Design Space in Network Processors, July 2005
  4. M.P. Dushyant, Performance Enhancement Schemes for Clustered Superscalar Processors, July 2005
  5. Vinodh Kumar R., Dynamic Path Profile Aided Recompilation in a Java Just-In-Time Compiler, January 2001
  6. Amit Rangari, Implementation of Simple COMA Simulator on RSIM, January 2000
  7. S.M. Sandhya, Instruction Scheduling Techniques in SUIF for Value Speculation, January 2000
  8. Veeral P. Shah, Copy Propagation Optimization and Linear Scan Register Allocation in JIT Compilation, January 2000
  9. V. Amar Nath, Performance Enhancement of Software Distributed Shared Memory, January 1999
  10. P. S. Udaya Shankara, Granularity Study and Evaluation of Performance Metrics for Shared Memory Accesses in Distributed Shared Memory Architectures, January 1999
  11. V. Kumar, Java Virtual Machine: Just-In-Time Compiler Implementation for SPARC, January 1999
  12. Amod K. Dani, Software Pipelining for VLIW Architectures, January 1997
  13. Biren Gandhi, Distributed Shared Memory on Network of Workstations with TCP/IP, January 1997
  14. B. Hari Krishna, Enhancing the Performance of Multithreaded Architectures, January 1997
  15. N.S.S. Narasimha Rao, Implementation of Three Software Pipelining Methods, January 1997
  16. S. Ramesh, DSM-SP2: An Implementation of Distributed Shared Memory on IBM SP2, January 1997

M.E. (Int.)

  1. Srinivasan, Compiler Optimizations in the Presence of Value Speculation, July 1999
  2. N. Sreraman, A Vectorizing Compiler for Exploiting Multimedia Extensions, July 1999
  3. Lakshmi, Performance Enhancement and Evaluation of DSM-SP2: A Distributed Shared Memory on IBM SP2, July 1997
Last updated: 3 August 2017