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Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Reconfigurable Encoding

Proceedings of the International Conference on Computer Aided Design (ICCAD-2001)
San Jose, November 2001


  1. Subash Chandar G., Texas Instruments India Ltd., Bangalore; Supercomputer Education and Research Center
  2. M. Mehendale, Texas Instruments India Ltd.
  3. R. Govindarajan, Supercomputer Education and Research Centre; Department of Computer Science and Automation


In this paper, we propose a reconfiguration mechanism that allows multiple instruction compression to reduce both code size, which in turn reduces the cost, and (instruction fetch) power, which enhances the battery lifetime, two key considerations in embedded DSP systems. We enhance Texas Instruments DSP core TMS320C27x to incorporate this mechanism and evaluate the improvements on code size and instruction fetch energy using real life embedded control application programs. We show that even with minimal hardware overhead, we can improve code size by over 10% and instruction fetch energy by over 40%.


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