Lab for High Performance Computing SERC, Indian Institute of Science
Home | People | Research | Awards/Honours | Publications | Lab Resources | Gallery | Contact Info | Sponsored Research
Tech. Reports | Conferences / Journals | Theses / Project Reports

An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures

Proceedings of the 16th International Conference on Compiler Construction (CC-2007)
Braga, Portugal, March 26--30, 2007


  1. K. Shyam, Supercomputer Education and Research Centre
  2. R. Govindarajan, Supercomputer Education and Research Centre; Department of Computer Science and Automation




Full Text