Packet Reordering in Network Processors

Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS-07)
Long Beach, CA, USA, March 26--30, 2007

Authors

1. S. Govind, Supercomputer Education and Research Center
2. R. Govindarajan, Supercomputer Education and Research Centre; Department of Computer Science and Automation
3. Joy Kuri, Centre for Electronics Design and Technology

Abstract

Network processors today consists of multiple parallel processors (microengines) with support for multiple threads to exploit packet level parallelism inherent in network workloads. With such concurrency, packet ordering at the output of the network processor cannot be guaranteed. This paper studies the effect of concurrency in network processors on packet ordering. We use a validated Petri net model of a commercial network processor, Intel IXP 2400, to determine the extent of packet reordering for IPv4 forwarding application. Our study indicates that in addition to the parallel processing in the network processor, the allocation scheme for the transmit buffer also adversely impacts packet ordering. In particular, our results reveal that these packet reordering results in a packet retransmission rate of up to 61%. We explore different transmit buffer allocation schemes namely, contiguous, strided, local, and global which reduces the packet retransmission to 24%. We propose an alternative scheme, Packet Sort, which guarantees complete packet ordering while achieving a throughput of 2.5 Gbps. Further, Packetsort outperforms the in-built packet ordering schemes in the IXP processor by up to 35%.

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