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A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Proceedings of the 21st Annual IEEE SoC Conference (SoCC-08)
Newport Beach, CA, USA, September 2008


  1. Sudhakar Surendran, Texas Instruments India Ltd.
  2. Rubin Parekhji, Texas Instruments India Ltd.
  3. R. Govindarajan, Supercomputer Education and Research Centre; Department of Computer Science and Automation


Verification is one of the important stages in designing an SoC (System on Chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.


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