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Region Based Structure Layout Optimization by Selective Data Copying

Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT-2009)
Raleigh, USA, August, 2009


  1. Sandya Mannarswamy, Department of Computer Science and Automation
  2. R. Govindarajan, Supercomputer Education and Research Centre; Department of Computer Science and Automation
  3. Rishi Surendran, Hewlett-Packard, India


As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to modify an application's data layout to improve cache locality and cache reuse. Whole program Structure Layout [WPSL] transformations can significantly increase the spatial locality of data and reduce the runtime of programs that use linked list-based data structures, by increasing the cache line utilization. However, in production compilers WPSL transformations do not realize the entire performance potential possible due to a number of factors. Structure layout decisions made on the basis of whole program aggregated affinity/hotness of structure fields can be suboptimal for local code regions. WPSL is also restricted in applicability in production compilers for type unsafe languages like C/C++ due to the extensive legality checks and field sensitive pointer analysis required over the entire application. In order to overcome the issues associated with WPSL, we propose Region Based Structure Layout (RBSL) optimization framework using selective data copying. We describe our RBSL framework, implemented in the production compiler for C/C++ on HP-UX IA-64. We show that acting in complement to the existing and mature WPSL transformation framework in our compiler, RBSL improves application performance in pointer intensive SPEC benchmarks ranging from 3% to 28% over WPSL.


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