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Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs

International Conference on Parallel Architectures and Compilation Techniques 2011
Galveston, TX, USA, October 10--14, 2011


  1. Nagendra Dwarakanath Gulur, Supercomputer Education and Research Centre
  2. R. Govindarajan, Supercomputer Education and Research Centre; Department of Computer Science and Automation


In this paper, based on the temporal and spatial locality characteristics of memory accesses in multicores, we propose a re-organization of the existing single large row- buffer in a DRAM bank into multiple smaller row-buffers. The proposed configuration helps improve the row hit rates and also brings down the energy required for row-activations. The ma- jor contribution of this work is proposing such a reorganization without requiring any significant changes to the existing widely accepted DRAM specifications. Our proposed reorganization improves performance by 35.8%, 14.5% and 21.6% in quad, eight and sixteen core workloads along with a 42%, 28% and 31% reduction in DRAM energy. Additionally, we introduce a NeedBasedAllocation scheme for buffer management that shows additional performance improvement.


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