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Power-Aware Compilation Techniques for Embedded Systems

MSc(Engg) Thesis, Supercomputer Education and Research Centre,
Indian Institute of Science, Bangalore, India, July 2006.


  1. Shyam Krishnaswamy, Supercomputer Education and Research Centre


The demand for devices like Personal Digital Assistants PDA?s, Laptops, Smart Mobile Phones, are at an all time high. As the demand for these devices increases, so is the push to provide sophisticated functionalities in these devices. However energy consumption has become a major constraint in providing increased functionality for these devices. A majority of applications meant for these devices like video recorder, voice recorder, camera capture, etc., deal with multimedia content. These applications are array dominated, highly data intensive and spend a major amount of their execution time and energy in the memory subsystem.

This thesis proposes compiler directed optimization technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture, having multiple memory banks, and various low-power operating modes for each of these banks. We propose an efficient layout of the data segment to reduce the number of simultaneously active memory banks, so that the other memory banks that are inactive can be put to low power modes to reduce the energy. We model this problem as a graph partitioning problem, and use well known heuristics to solve the same. We also propose a simple Integer Linear Programming (ILP) formulation for the above problem. Preliminary results indicate that we are able to obtain, on an average, substantial energy reduction over the base scheme, and considerable energy reduction over previously suggested methods. Also, our results are well within the optimal results obtained by using ILP method.

In this thesis we also investigate a combined hardware and software approach to reduce the energy consumed by the system. Dynamic voltage and frequency scaling has been identified as one of the effective approaches in this regard. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. We concentrate on coarser program regions and for the first time uses program phase behaviour for performing dynamic voltage scaling. We relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple Integer Linear Program (ILP) formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains sizeable reduction in energy consumption on an average, with a negligible performance degradation. Further the energy consumed by our heuristic solution is well within the optimal solution obtained from the ILP approach.


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