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A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

MSc(Engg) Thesis, Supercomputer Education and Research Centre,
Indian Institute of Science, Bangalore, India, November 2006.


  1. Sudhakar Surendran, Supercomputer Education and Research Centre


SoCs (System on Chips) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC. Verification is the process of checking if the transformation from architectural specification to design implementation is correct. Verification involves creating the following components: (i) a test-plan that identifies the conditions to be verified, (ii) a test-case that generates the stimuli to verify the conditions identified, and (iii) a test-bench that applies the stimuli and monitors the output from the design.

Verification consumes upto 70% of the total design time. This is largely due to the complex and manual nature of the verification task. To reduce the time spent in verifying the design, the components used for verification can be generated automatically or created at an abstract level (to reduce the complexity) and re-used.

In this work we present a methodology to synthesize test-cases from re-usable code segments and abstract specifications. Our methodology consists of the following major steps: (i) identifying the structure of test-cases, (ii) identifying code segments of test-cases that can be re-used from one SoC to another, (iii) identifying properties of an SoC and its modules that can be used to synthesize the SoC specific code segments of the test-case, and (iv) proposing a synthesizer that uses the code segments, the properties and the abstract specification to synthesize test-cases.

We discuss two specific classes of test-cases. These are test-cases for verifying the memory modules and the test-cases for verifying the data transfer modules. These are considered since they form a significantly large subset of the device functionality. We implement a prototype test-case generator and also present an example to illustrate the use of methodology for each of these classes. The use of our methodology enables (i) the creation of test-cases automatically that are correct by construction and (ii) re-use of the test-case code segments from one SoC to another. Some of the properties (of the modules and the SoC) presented in our work can be easily made part of the architectural specification, and hence, can further reduce the effort needed to create them.


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