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PhD Thesis, Supercomputer Education and Research Centre,
Indian Institute of Science, Bangalore, India, September 2008.
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the area, power and performance of the entire system. Further, the memory subsystem constitutes a large part (typically up to 70%) of the silicon area for the current day SoC.
The organization of on-chip memory in embedded processors varies widely from one SoC to another, depending on the application and market segment for which the SoC is deployed. There is a wide variety of choices available for the embedded designers, starting from simple on-chip SPRAM based architecture to more complex cache-SPRAM based hybrid architecture. Hence the embedded system designer is forced to perform complete memory architecture exploration. A designer is interested in multiple optimal design points to address different market segments. Due to its large impact on system performance parameters, the memory architecture is often hand-crafted by the designer based on the targeted applications. However, with the combination of on-chip SPRAM and cache, the memory design space is too large for manual analysis.
In this work, we propose an automated framework for on-chip memory architecture exploration. The proposed framework integrates memory architecture exploration and data layout to search the design space efficiently. While the memory exploration selects specific memory architectures, data layout efficiently maps the given application on to the memory architecture under consideration and thus helps in evaluating the memory architecture. Data layout partitions data variables among multiple memory banks with an objective to reduce bank conflicts and this is a NP-complete problem. We have proposed a fast and efficient heuristic for the data layout that can be used for memory architecture exploration. Further, we have proposed a memory exploration framework at both logical and physical memory architecture levels. At logical memory archhitecture level, with practical constraints imposed, the design space is of the order of 100,000+ unique architectures for the target architecture considered by us. However, at the physical memory architecture level, the design search space is much larger at least by one to two orders of magnitude. Our work addresses on-chip memory architecture for DSP processors; such memories are organized into multiple memory banks, where each back can be a single/dual port banks with non-uniform bank sizes. Our work addresses memory architecture exploration for on-chip memory architectures that is both SPRAM-based and cache-based. Our proposed method is based on a multi-objective Genetic Algorithm, and outputs several hundred Pareto-optimal design solutions which are interesting from an area, power and performance viewpoint.